1. Field of the Invention
The present invention relates to an information processing apparatus comprising an external input/output mechanism capable of carrying out write or read at a high speed between a memory device provided in a processor and an outside, and a memory access arranging method in the case in which a contention of access to the memory device is generated.
2. Description of the Related Art
In the case in which write/read to/from one memory device is to be carried out by a plurality of control devices, conventionally, a dual port memory is used as the easiest implementing method. In recent years, however, importance has been attached to a system LSI in an LSI market and the scale of a circuit has been increased. For this reason, the dual port memory occupying a large chip area is disadvantageous in respect of a cost in the system LSI requiring a memory having a large capacity. Therefore, it can be proposed that a single port memory is used in order to reduce the chip area. Depending on a timing for giving access from a plurality of control devices, however, the contention of the access is generated. For this reason, it is necessary to arrange the access.
As a method of arranging access given from a plurality of control devices, conventionally, the access is arranged in the following manner. In the case in which access is given from a second control device having a higher priority than that of a first control device while the first control device gives access to a memory, the second control device is caused to wait (stand by) until the access of the first control device to the memory is ended. When the access of the first control device to the memory is ended, access is started to be given from the second control device to the memory. Moreover, the access of the first control device to the memory is entirely prohibited while the access is given from the second control device to the memory. Consequently, the second control device can give access to the memory with a priority over the first control device (for example, see JP-A-9-198298).
More specifically, during the execution of the access by the control device which first gives access, the control device giving access later cannot give access to the memory until the access of the control device which first gives access is ended.
However, it is supposed that access is to be given with a priority from any of the control devices. For example, in the case in which access is given from an external processor through an external input/output mechanism to a processor built-in memory, for example, the access given from the external processor to the processor built-in memory does not take a long time. However, the external processor requires a high-speed operation. For this reason, it has been demanded to always give access from the external processor with a priority.
In the application of the technique described above to a processor comprising the external input/output mechanism requiring high-speed access to the memory provided in the processor, when access from the external input/output mechanism to the memory is generated while a processor core gives access to the memory, the external input/output mechanism is caused to wait until the access of the processor core is ended. Consequently, the access speed of the external input/output mechanism is reduced.
More specifically, the access speed of the external input/output mechanism is reduced depending on the state of access of the processor to the memory in some cases. In the casein which this mechanism is applied to a data transfer through the external input/output mechanism from the external processor to the memory provided in the processor, accordingly, an external access speed is reduced, and furthermore, the operating speed of a final set is also reduced.